1. Field of the Invention
The present invention relates to an analog duty cycle correction loop that uses clock averaging and clock/voltage comparisons to determine whether a delay should be increased or decreased for a reference clock.
2. Related Art
Innumerable applications using clocks rely on a controlled clock duty cycle for optimal performance. Generally, a 50% duty cycle, in which a waveform has equal high and low portions, is considered desirable. Known duty cycle correction techniques use either a phase-locked loop (PLL) or a delay line loop (DLL) to double an input clock frequency, and then use a divide-by-two circuit to generate the desired frequency with a corrected duty cycle.
For example, FIG. 1 illustrates a known duty cycle correction circuit including a clock chopper circuit 101, a duty cycle comparator circuit 102, and a delay control circuit 103. Duty cycle comparator circuit 102 generates a square wave with a 50% duty cycle at one-half the input frequency (i.e. the digital clock) using a frequency divider 104, and then compares that square wave with the duty cycle corrected output clock (DCOUT). Delay control circuit 103 uses the output of duty cycle comparator circuit 102 to control clock chopper circuit 101. Clock chopper circuit 101 includes both coarse delay elements and fine delay elements that can form an adjustable delay. U.S. Pat. No. 5,757,218, which issued to Blum on May 26, 1998, describes this duty cycle correction circuit in greater detail. Notably, Blum is limited to correcting the duty cycle using digital delay elements.
Some applications may require or may benefit from an analog loop instead of a fully digital loop. Therefore, a need arises for a duty cycle correction technique/circuit using analog delay elements.